The subject matter of this application is related to the subject matter in a co-pending non-provisional application by the same inventor(s) as the instant application and filed on the same day as the instant application entitled, xe2x80x9cApparatus for Supporting Multiple Delayed Read Transactions Between Computer Buses,xe2x80x9d having Ser. No. 09/352,720, and filing date Jul. 13, 1999.
The present invention relates to the design of computer system buses for transferring data between computer system components. More specifically, the present invention relates to a system that supports multiple delayed read transactions between computer buses.
In order to improve computer system performance, some processors, such as the Intel Pentium, are designed to drive an additional request across a computer system bus before the current bus request is completed. This technique is known as xe2x80x9cbus pipelining.xe2x80x9d (The Intel Pentium is manufactured by the Intel Corporation of Santa Clara, Calif.
Bus pipelining improves computer system performance because more than one bus transaction can be processed at the same time. However, this performance advantage can be lost when both requests are read operations directed from a processor bus, such as the Pentium Processor Bus, to a peripheral bus, such as the PCI bus. This is due to the fact that on certain peripheral buses, such as the PCI bus, a bus master can send a retry command back to the processor if the current request is delayed or cannot otherwise be completed immediately. When such a retry command is received by a processor bus, such as the Pentium Processor Bus, the retry command causes both the current request and the pipelined request to be terminated and re-attempted by the processor. (The term xe2x80x9cPentium Processor Busxe2x80x9d as used in this specification refers to a bus adhering to the protocol described in Volume 1 of the xe2x80x9cThe Pentium Family Developer""s Manual,xe2x80x9d published in 1995 by the Intel Corporation.)
Consequently, in order to maintain ordering of transactions on the processor bus, the pipelined read request cannot be given to the peripheral bus until the current read request is guaranteed to complete. This removes the performance advantage of pipelining.
What is needed is a system that allows a pipelined read request to proceed in parallel with a current read request on a peripheral bus in spite of the fact that a retry on a processor bus causes all requests on the processor bus to be terminated and retried.
One embodiment of the present invention provides a method that supports multiple delayed read transactions between a host bus and a peripheral bus in a computer system. The method operates by receiving a first request from the host bus that is directed to the peripheral bus. The first request is stored in a first buffer and sent to the peripheral bus, so that the first request will be processed when the peripheral bus becomes available. If the first request is a read operation, the system waits to receive a pipelined request that is a read operation from the host bus that is directed to the peripheral bus. If such a pipelined request is received, the system stores the pipelined request in a second buffer, and sends the pipelined request to the peripheral bus, so that the pipelined request will be processed when the peripheral bus becomes available. Next, the system issues a retry request across the host bus. This retry request causes both the first request and the pipelined request to be retried at a later time on the host bus so that the host bus can be freed up for other transactions while the first request and the pipelined request are in process on the peripheral bus.
In one embodiment of the present invention, if the first request is a read operation that was previously requested, the system determines if read data from the previous request has been returned by the peripheral bus. If so, the system returns the read data across the host bus to complete the first request. Otherwise, the system issues a retry request across the host bus to cause the first request to be retried at a later time.
In one embodiment of the present invention, waiting to receive the pipelined request includes waiting a predetermined amount of time for the pipelined request. In a variation on this embodiment, this includes accessing a programmable counter containing the predetermined amount of time.
In one embodiment of the present invention, the first buffer and the second buffer are located on a host bridge that couples together the host bus and the peripheral bus. In a variation on this embodiment, the host bridge includes a host slave module that acts as a slave device on the host bus, and a peripheral master module that acts as a master device on the peripheral bus.
In one embodiment of the present invention, the system receives a programmable delay enable signal that enables delayed read operations.